A CAN is an International Standards Organization (ISO)-defined serial data communications bus topology and associated peer-to-peer message-based protocol. The CAN bus is used commercially in automotive, aerospace, maritime and a variety of industrial applications. Additional information regarding the CAN bus may be found in ISO 11898-1: 2003, “Road vehicles—Controller area network (CAN)—Part 1: Data link layer and physical signaling” (confirmed 2009); ISO 11898-2: 2003, “Road vehicles—Controller area network (CAN)—Part 2: High-speed medium access unit” (confirmed 2009); and ISO 11898-5: 2007, “Road vehicles—Controller area network (CAN)—Part 5: High-speed medium access unit with low-power mode” (confirmed 2009).
FIG. 1 is a prior-art diagram illustrating a CAN bus 104 and CAN node architecture 107. One or more nodal devices (e.g., the nodal device 109) associated with each node (e.g., the node 110) such as sensors, actuators, switches, and other control devices typically communicate with each other across the CAN bus 104. Each such nodal device accesses the CAN bus 104 as a sender and/or receiver via a node microcontroller (e.g., the microcontroller 112), a CAN bus node controller (e.g., the CAN controller 115), and a CAN bus differential transceiver (e.g., the CAN transceiver 120).
Termination resistors 130A and 130B, typically 120 ohms each, are positioned at the far ends of the CAN bus 104 to reduce signal reflections and to provide a current path for the differential signal produced by a transmitting CAN transceiver. Other CAN bus impedance elements include the input resistance of each nodal CAN transceiver. A receiver portion of each CAN transceiver presents a high resistance (e.g., the resistance 135 associated with the transceiver 120) across the CAN bus 104 in parallel with the termination resistors 130A and 130B.
Additionally, the wires themselves associated with the CAN bus 104 create a distributed parasitic capacitance (e.g., the capacitance C(D) 140) across the bus 104. The RC time constant of the distributed capacitance 140 in parallel with the combined parallel resistances across the bus 104 may have a significant effect on the shape of CAN bus signals, particularly for bus lengths of many meters with many attached bus nodes, as further described below.
FIG. 2 is a prior-art diagram illustrating a CAN data frame 200. An arbitration field 215 within the data frame 200 includes a dominant-low destination node address assigned to the data frame 200. The lowest binary address has the most dominant (logic zero) high-order bits and the highest priority. CAN nodes contend for the opportunity to transmit a data frame according to a CAN transceiver mechanism referred to as bitwise priority-based bus arbitration. When two or more nodes attempt to transmit data frames on the bus 104 simultaneously, a dominant bit in the arbitration field from one of the contending frames overwrites a recessive bit from another of the contending frames. Once this arbitration/contention process completes for the arbitration field 215, the node transmitting the CAN frame with the highest priority address wins the arbitration and continues transmitting that frame. The other nodes that were attempting to simultaneously transmit a frame perform a back off and the remainder of the arbitration-winning frame is transmitted without further interference from other nodes.
Waveform shapes of the differential signals appearing on the bus 104 during the arbitration portion of the CAN frame are particularly important to ensure the integrity of the arbitration process. Such arbitration-time waveform shapes are frequency dependent in the presence of the above-described bus impedance considerations and ultimately limit CAN bus bandwidth, bus length, and the maximum number of attached nodes. An enhanced CAN technique referred to as “CAN with Flexible Data-Rate” or simply “CAN FD” has been proposed and is in the process of being commercially implemented. Additional information regarding CAN FD may be found in a specification, “CAN with Flexible Data-Rate” Version 1.0 (Released Apr. 17, 2012)© Copyright 2011, Robert Bosch GmbH, Robert Bosch Platz 1, 70839 Gerlingen, Germany, and located at: http://www.bosch-semiconductors.de/en/ubk semiconductors/safe/ip_modules/can_fd/can.html as of Nov. 18, 2013.
Among other considerations, CAN FD proposes transmitting flexible data rate (FD) portions 230 of the data frame 200 with shorter-than-normal bit-time periods. It is noted that a bit time period is referred to herein as a “tbit”. The FD portions 230 of the data frame 200 are not involved with arbitration or other bus-sensitive processes during which multiple nodes could attempt to exert the bus 104. Thus, operation in CAN FD mode results in a higher-than-normal bit rate during the FD portions 230 of the data frame 200 and the possibility of higher-than-normal throughput as compared to operation in CAN standard mode.
FIG. 3 is a prior-art diagram illustrating an idealized CAN bus differential waveform 300. The waveform 300 is representative of an idealized CAN bus signal resulting from a transmitting CAN transceiver (e.g., the transceiver 120 of FIG. 1) operating with power supply rails of Vcc equal to 5 volts and ground. An active CAN transceiver drives the waveform 300 to a “dominant” state representing a logic LOW level (logic zero). CAN bus transceivers are biased at approximately Vcc/2 such that the differential waveform peaks CANH 320 and CANL 325 avoid distortion by not approaching the supply voltage rails. A CAN bus logic HIGH “recessive” level 340 results when bus transceiver drivers are inactivated and remove their respective differential output voltages from the bus 104.
FIG. 4 is a prior-art diagram illustrating a CAN bus differential waveform 400 affected by bus RC time constant constraints. In particular, the dominant-to recessive decay time 415 of the falling edge 420 of the waveform 400 to the maximum recessive differential voltage 430 is considerably longer than that of the idealized bus waveform 300 of FIG. 3. The longer decay time 415 is due to the charge stored in the previously-described parasitic capacitance across the bus 104. The residual charge tends to maintain the dominant-state differential voltage across the bus 104 and extend the dominant-to-recessive period during which the bus 104 remains in an ambiguous state and therefor cannot be sampled to determine whether or not a state change has occurred.
The sampling point 440 configured in the bus node controller connected to the bus transceiver is nominally set at approximately 75% into the tbit period 435. Once a node has won arbitration, it is responsible for transmitting the remainder of the CAN frame. The transmitting node controller compares what is being sent on TxD to what is being received. If the data received is different from that sent, the controller will interpret such condition as a transmit error. The transmit error condition will initiate an error frame transmission instead of transmitting the remainder of the data frame. Thus, if the dominant to recessive edge delay time 415 extends to the point 450 where the bus waveforms cross the recessive threshold 430 after the sampling point 440, bus errors will be generated and throughput will suffer. This phenomenon establishes a maximum data rate for a given bus impedance using standard CAN protocols and methods.